Full adder (AND–OR–NOT): one gate delay per step
a = 0
b = 0
c = 0
Replay
a
b
cₙ
a
b
cₙ
a
b
cₙ
a
b
cₙ
a
b
b
cₙ
a
cₙ
S
0
cₙ₊₁
0
(a) sum
(b) carry